DAC 2016 Panel:

VARIATION-AWARE DESIGN AT ADVANCED & LOW-POWER PROCESSES
- Monday, June 6, 2016, 10:30 AM - 11:30 AM
- Room 9BC, Austin Convention Center, Austin, TX

Opening by Amit Gupta (CEO, Solido) on Custom IC design market data

Panelists:

Azeez Bhavnagarwala - ARM, Inc., San Jose, CA
Glen Wiedemeier - IBM Corp., Austin, TX
John Barth - Invecas, Williston, Vermont
Jeff Dyck - Solido Design Automation, Inc., Saskatoon, Canada

Variation effects have an ever greater impact on low-power, low-voltage processes and advanced FinFET/FDSOI nodes; at each, new sources of variation must be considered. Furthermore, increased competition is forcing tighter design margins to make high-performance, low-power, low-cost products. Designers must do more variation analysis than ever to achieve these tighter margins, using advanced variation-aware technology for speed, accuracy and coverage to deliver competitive chips on schedule.

The panel discussion will focus on recent, highly effective ways to address variation-aware design for Memory, Analog/RF and Standard Cell design. The methodologies will include high-sigma Monte Carlo, PVT, statistical PVT, and hierarchical Monte Carlo.